ESD Challenges

General Discussion

Even experts in the field of ESD design, testing and failure analyses have difficulty in the accurate use of the words "always," "never," "all," "none" and "I know." Because of the nature of ESD energy, ESD protection circuitry needs to be re-examined every time semiconductor technology changes. The key characteristic of ESD energy (just as with lightning) is that it will follow the path of least resistance. Therefore in order to guarantee that an integrated circuit meets customers’ robust ESD requirements, extensive testing through all possible pin-to-pin combinations must be performed.

It is also important to understand that good ESD protection is achieved by making good IC-level design decisions, not just an I/O pad design decision. Those IC-level design decisions involve how a given pad ring is designed as well has how the core components of the IC design interconnect to the outside world through the pad ring. This has become particularly important as more analog circuitry has been brought on-chip and RF functions have been integrated into the single IC with the advent of SiGe technologies.

The key to good ESD design is to predict the paths that the ESD energy might flow and then either manage the current flow or provide an alternate path for the current to flow. Because of the high voltages, it is almost never an option to block the ESD energy. The key to current-flow management is power management. Because ESD energy is stored on a capacitor of known size at a known voltage, the total energy that is being discharged through the device is known. The sudden discharge of this energy causes significant voltage transients as well as concentrated power that creates hot spots within the integrated circuit. These two items (voltage and power) cause nearly all the failures identified in ESD testing. Therefore prediction and management of the high current flow is key to good protection. High voltages cannot be allowed across the ultra-thin gate oxides, and power must be spread out (i.e., distributed).

There are three basic types of failures:

• Oxide "punch-through" (primarily gate oxide, but occasionally field or inter-level oxide)
• Fused "open" conductors (poly or metal)
• Leakage or shorts caused by localized heating (the dominant observed failure)

As semiconductor technology advances into the deep-submicron arena, transistors continue to shrink in gate thickness, transistor length, transistor widths, dielectric insulator thickness, conductor thickness and device/conductor spacings. In addition to shrinking, new conductors and materials are being introduced to provide additional capability. All of these changes can and do affect ESD performance (i.e., tolerance). (Please note that dimensions are generic and not specific to any foundry.)